一种改进运放共享结构的11位流水线ADC设计

Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration

对流水线模数转换器(ADC)的运放共享结构进行了改进,设计了一款应用于超高频RFID系统的11位100 MS/s采样率的流水线ADC.该ADC将采样保持电路和第一级余量增益电路共享同一个运算放大器,从而提高运算放大器的电流效率,进而减小功耗.运算放大器采用两对差分输入一对差分输出的、带增益自举的直筒式结构.通过使用对称栅压自举开关,减小了连接虚地的开关,流过大电流时,注入电荷的失配.采用此运放共享思路设计的11位流水线ADC,在奈奎斯特采样时,有效位数是10.6bit,SFDR为71.2dB,SNDR为65.5dB,功耗为52mW.

This paper presents the improvement of the OPAMP sharing configuration for the pipelined analog to digital converter （ADC）, and designs an 11-bit and 100 MS/s sampling-rate pipeline ADC for a UHF RF1D system. The sample and hold circuit shares the same OPAMP with the first-stage residual gain amplifier circuit, so that current efficiency of OPAMP is improved and power consumption is saved. The OPAMP adopts gain-boost telescope structure with two pairs input and one pair output. By using symmetrical bootstrapped switch, the charge injection mismatch is reduced, when large current flows into virtual ground. The pipeline ADC achieves an ENOB of 10. 6 bits, an SFDR of 71.2 dB, an SNDR of 65.5 dB and power consumption of 52 mW at the Nyquist sampling input frequency.