一种使用增益校准技术的ΔΣ时间数字转换器

A ΔΣ Time-to-Digital Converter Based on Gated-Ring-Oscillator Using Time Amplifier Gain Calibration Technique

提出了一种使用门控环形振荡器及级间增益误差校正技术的1-1MASH结构ΔΣ型TDC.该TDC使用两个GRO-TDC级联,实现二阶噪声整形.采用基于电荷泵的大增益时间放大器进行级间放大,进一步降低了TDC的量化噪声.使用一种级间增益校准技术校正时间放大器增益误差与两级GRO的频率失配.该TDC在SMIC 40nm 1P8M CMOS工艺下设计和仿真,实现了宽带宽、高精度(低带内积分噪声)、大动态范围.

A 1-1 MASH delta-sigma time-to-digital converter using charge-pump based time-amplifier and gain calibration technique is proposed. The TDC using two cascaded gated-ring-oscillator based TDCs and achieved 2nd order noise shaping. By adopting of a high gain charge-pump based time amplifier, the quantization noise of proposed TDC is further diminished. The proposed TDC is designed and simulated on SMIC 40 nm 1P8M CMOS process, achieved high bandwidth, high resolution （low integrated noise） and large dynamic range.