摘要
针对宽带高速数据传输需求,提出了一种利用FPGA内部Select IO资源实现SERDES高速传输的解决方法。通过对OSERDES和ISERDES原语的使用来实现对数据的并串转换和串并转换。在实际工程应用中实现了对32个通路、每路400 Mb/s的稳定传输,验证了系统的有效性与可靠性,满足了项目需求。该设计易于移植,对于高速、多路数据传输系统的设计具有一定参考意义。
According to the demand of high-speed wideband data transmission, a solution to the re- alization of the SERDES-based high-speed transmission is proposed making use of the SelectlO re- sources in the FPGA. The parallel and serial data conversion is realized through the OSERDES and ISERDES primitives. In the practical engineering application, 32-channel data transmission is sta- ble, with the speed of 400 Mb/s per channel, verifying the effectiveness and reliability of the system and saisfying value for the the requirements of the project. The design is easy to transplant and has a reference design of high-speed, multi-channel data transmission systems.
出处
《雷达与对抗》
2016年第2期38-42,共5页
Radar & ECM
