一种4路正交时钟校准电路的设计

Design of a Four-Path Orthogonal Clock Corrector

采用TSMC 40nm CMOS工艺,设计了一种正交时钟校准电路,它包含2个脉冲宽度调整环路和1个内嵌的延迟锁相环。与其他校准电路相比,本文校准电路无需50%占空比的参考时钟或者单端转差分（STC）电路,就能获得4路占空比为50%的时钟,还能调整时钟的相对相位以输出4路正交时钟。当工作频率为3.125GHz时,该校准电路能将占空比为10%～90%的输入时钟自动调整至占空比为50%±0.2%的时钟,相位调整范围为58°～122°,电路功耗为2.2mW,可应用于RapidIO物理层接收机电路中。

An orthogonal clock correction circuit with two pulse width control loops（PWCL）and an embedded delay-lock loop（DLL）was designed in the TSMC 40 nm CMOS process.The proposed circuit could generate not only 4-path 50% duty cycle clocks,but also 4-path orthogonal output clocks by adjusting the relative phase of clock.In comparison with other architectures,neither reference clock of 50 % duty cycle nor single-to-complementary（STC）circuit was needed.The simulation results showed that the 10%-90% duty cycles of the output could be adjusted automatically to 50%±0.2%,and the adjustable phase range was 58°to 122°at an operating frequency of3.125 GHz.The power consumption was 2.2mW.The proposed circuit could be applied to RapidIO physical layer interface receiver.