基于单轮循环结构的SMS4加密芯片的研究与设计

Research and design of SMS4 cryptographic chip based on full iteration architecture

文章在分析SMS4原理的基础上提出了一种基于单轮循环结构的SMS4加密方案,通过复用单一的加密单元,经过32次循环迭代完成加密,大大减少了硬件资源的使用。该设计的开发平台是Altera公司的Quartus II 9.0,使用的FPGA(Field-Programmable Gate Array)开发板是Cyclone II EP2C8Q208C8。运行结果表明,SMS4加密芯片使用了5 268个逻辑单元和139 264位存储器资源,系统的时钟频率可以达到51.35 MHz,信息加/解密的峰值速度为3.2Gb/s,系统功耗为132.30 m W。

Based on analyzing the principle of SMS4,the paper puts forward a scheme of SMS4 cryptographic chip based on full iteration architecture.By multiplexing a single encryption unit,the design completes encryption after loop iteration 32 rounds, thus it greatly reduces the consumption of resources.This design＇s development platform is the Quartus Ⅱ 9.0 of Altera company, the FPGA（Field-Programmable Gate Array）development board is the Cyclone Ⅱ EP2C8Q208CS.The results shows ： this design only uses 5 268 logic elements and 139 264 memory bits, the highest clock frequency is up to 51.35 MHz, the encryption speed is up to 3.2 Gb/s, and the power of the system is 132.30 mW.