基于高级综合技术的RS算法实现

Implementation of RS Algorithm Based on High-Level Synthesis

随着SoC技术的不断发展以及集成应用设计规模和复杂度的不断提升,使用传统的RTL设计方法难度越来越大。高级综合技术(High-level synthesis,HLS)可以实现将C语言描述的算法级设计自动转换成HDL语言描述的寄存器级设计。使用Synphony C Compiler综合工具进行RS编、译码算法设计,利用综合工具快速的架构探索以及高效的验证方法,在综合性能、面积、功耗等要求之后,完成算法C语言到Verilog HDL语言的快速转换。这种设计方法大大缩短了设计周期。

With the rapid development of the System on Chip （ SoC ） technology and the increasing design scale and complexity of integrated applications, there are more difficulties for design at register-transfer level. High-level synthesis raises the design abstraction level to algorithm level and allows rapid generation of optimized RTL hardware Usually, we use C language to describe the algorithm level design and Verilog HDL language to describe the regis- ter-transfer level design. Synphony C Compiler tool can offer the advantages of rapid architecture exploration and unified verification at the design of hardware of encoding and decoding based on Reed-Solomon code. It can generate RTL that is optimized for performance, area, and power requirements, and greatly shorten design cycle