基于CPLD的多电源上电时序的控制设计

Supply Voltage Sequence Control Design Based on CPLD

随着高速数字信号的快速发展,对集成多核和高速接口的处理器的电源的上电时序的设计则越来越重要,严格的上电时序保证了器件免受损坏和进入良好的工作状态;基于CPLD的多电源上电时序的控制设计则更加可靠、稳定、精确。

With the rapid development of high speed digital signal,the integration of multi cores and high speed interface processors on the supply voltage sequence is more and more important,strict sequencing could ensure the devices from damage and enter a better working condition;Supply voltage sequence control design based on CPLD is more reliable,stable and accurate.