基于标志编码的指令Cache低功耗方法

Tag Encoding Based Low Power Instruction Cache

针对嵌入式处理器中指令Cache功耗显著的问题,提出了一种基于标志编码的低功耗指令Cache设计方法.通过增加一个容量很小的标志缓冲器来保存内核地址中的标志位,并利用位宽较小的标志编码存储器取代传统指令Cache结构中位宽较大的标志存储器来存储标志缓冲器中每一行对应的编码数据,减小了指令Cache的面积,从而降低了每次访问指令Cache的功耗.实验结果表明,本文提出的指令Cache结构相比传统指令Cache结构功耗降低了11.76%,面积减小了10.04%.

Instruction cache dissipates a large amount o{ energy in embedded processor. This paper proposes a low power design method for instruction cache based on tag encoding. Adding a tag buffer with small size to store the tag bits of instruction fetch address, and replacing the tag store with large bit wide in the traditional instruction cache with the tag encoding store with little bit wide to store the encoding data of the tag buffer line. This method can reduce the instruction cache area, thus saving the instruction cache power consumption. Experimental results show that this method could save 11.76% of instruction cache power consumption and reduce 10. 04 % of instruction cache area, in comparison with the traditional instruction cache.