基于Pareto支配的MPRM电路面积与可靠性优化

Pareto Dominance Based Area and Reliability Optimization of MPRM Circuits

针对MPRM(Mixed-Polarity Reed-Muller)电路的面积与可靠性折中优化问题,在逻辑级建立面积估算模型以及电路SER(Soft Error Rate)解析评价模型,并采用Pareto支配概念对MPRM电路进行面积与可靠性多目标优化.通过对MPRM电路的XOR部分进行树形异或门分解,并考虑多个输出之间异或门的共享,建立面积估算模型.采用信号概率和故障传播方法,并考虑电路中的逻辑屏蔽因素以及信号相关性,建立电路SER解析评价模型.根据所提出的面积和SER评价模型,采用极性向量的格雷码序穷举搜索MPRM的极性空间得到MPRM电路面积与可靠性的Pareto最优解集,并使用效率因子技术指标选取最终解.MCNC基准电路的实验结果表明,与面积最小MPRM电路相比,所选取的MPRM电路可以在较小面积开销的前提下获得较高电路可靠性.

Area and SER （ Soft Error Rate） evaluation models at logic level are proposed for area and reliability opti- mization of MPRM （Mixed-Polarity Reed-Muller） circuits, the trade-off between area and reliability is achieved by using Pareto dominance based multiobjective optimization. The area is computed by decomposing the XOR part of MPRM circuit as trees Of XOR gates and counting in XOR gate sharing among multiple outputs. The SER is computed by using signal probability and fault propagation techniques, and taking into account the logic masking effects and correlations among signals in the circuit network. Based on the proposed area and SER evaluation models, the Pareto optimal set for area and SER of MPRM circuit is obtained by using polarity optimization method with Gray code based exhaustive search strategy, the final solution is selected by using a mettle called efficiency factor. Experimental results by using a set of benchmark circuits from MCNC show that,in comparison with the MPRM circuits with minimized area, the selected MPRM circuits have improved reliability with less area overhead.