RTL综合中FPGA片上RAM工艺映射

Technology Mapping of FPGA on-Chip-RAM in RTL Synthesis

RAM(Random-Access-Memory,随机存储器)是FPGA(Field Programmable Gate Arrays)片上最重要的宏单元之一,RTL(Register-Transfer-Level)综合对FPGA开发中RAM的有效利用起至关重要作用.本文针对RTL综合中RAM源描述和目标结构多样化带来的技术难题,提出了一种RAM工艺映射方法,即建立工艺无关的RAM统一模型,在模型基础上通过建模、模式匹配、造价计算、绑定四步实现.该方法应用于RTL综合,可以将多种RAM源描述有效地映射到最佳类型和数量的FPGA片上RAM资源.实验数据表明采用该方法实现的RAM工艺映射效果和主流FPGA综合工具——Synplify和XST相当,该模块已经集成在自主开发的RTL综合工具——Hqsyn中并实现商用.

RAM is one of the most important macro-cells of FPGA, and RTL synthesis plays a critical role on the ef- fective use of RAM resources in FPGA development. For the difficulty of multi-resources and multi-targets in RAM technol- ogy mapping of RTL synthesis, this paper presents a method of technology mapping for FPGA on-chip RAM. In this meth- od, an unified technology-independent RAM model is proposed, and based on this model, RAM technology mapping is per- formed through a series of steps, including model set-up, mode-matching, cost calculation, and binding. When applied in RTL synthesis, this method is capable of mapping various styles of RAM RTL descriptions into the most appropriate type and number of FPGA on-chip RAM resources. Experimental result shows that this method achieves comparable RAM mapping results as the mainstream FPGA RTL synthesis tools-Synplify and XST, this technology has been integrated into the self-de- veloped RTL synthesis-Hqsyn and has been applied into the FPGA market.