期刊文献+

面向可重构系统的负载均衡低能耗调度算法 被引量:4

Load-balancing based energy-efficient scheduling algorithm for reconfigurable systems
下载PDF
导出
摘要 主要研究了基于多FPGAs部件的可重构系统高能耗问题。首先,对多FPGAs部件可重构系统的特征进行了建模,包括重构端口受限、资源受限及通信开销等建立了问题模型;接着,基于概率论与统计学的离散方差理论,采用负载均衡思想设计和实现了一种低能耗调度算法MLB。它的原理是通过计算各个FPGA部件的总能耗方差来引导负载的均衡分配。最后,通过模拟仿真实验,将提出的MLB算法分别与贪心算法和最新研究MFIT算法进行了比较,结果表明提出的算法复杂度低、运行速度快,不仅多节约了15%的能量,而且缩短了最大完成时间。 This paper studies the crucial problem of energy-efficiency on multi-FPGA based reconfigurable systems. Firstly, based on the characteristics of limited reconfiguration ports, resources and communication cost on reconfigurable systems, it establishes the problem model. Then, due to the importance of load-balancing for energy reduction, based on the probability theory and statistics, a loading balance algorithm for energy optimization(MLB)is proposed to address the high energy consumption problem. At last, it develops comprehensive trace-driven simulation experiments to evaluate the algorithm, the results show that the proposed algorithm is high efficiency with low-complexity. Compared with Greedy and the latest MFIT, MLB saves 15%energy more than that of two algorithms. Also, MLB shortens the maximum makespan.
作者 敬超
出处 《计算机工程与应用》 CSCD 北大核心 2016年第23期6-11,共6页 Computer Engineering and Applications
基金 国家自然科学基金(No.61563012 No.61540054) 广西自然科学基金(No.2015GXNSFBA139260) 桂林理工大学科研启动基金(No.002401003456) "嵌入式技术与智能信息处理"广西高校重点实验室主任基金(No.2016-01-05)
关键词 可重构系统 多现场可编程门阵列(FPGAs)部件 负载均衡 低能耗调度 reconfigurable system multiple Field-Programmable Gate Arrays(FPGAs) load balancing energy-efficient scheduling
  • 相关文献

参考文献1

二级参考文献7

  • 1C F Li. Post-placement leakage optimization for partial- ly dynamically reconfigurable FPGAs[C]// Proc Inter- national Symposium on Low Power Electronics and De- sign (ISLPED) Portland, oregon, USA: IEEE, 2007.
  • 2Perng N C . Energy-efficient scheduling on multi-con- text FPGA's[C]//Proc International Symposium on Circuits and Systems (ISCAS) Island of KOS, Greece: IEEE, 2006.
  • 3Angermeier J. Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads [C]//Proc IEEE Reconfigurable Architecture Work- shop (RAW) on IPDPS miami, Florida, USA: IEEE, 2008.
  • 4Li F. Architecture evaluation for power-efficient FP- GAs [ C]// Proc ACM International Symposium on Field-Programmable Gate Arrays (FPGA) Monterey, CA, USA: ACM, 2003.
  • 5Li F. Low-power FPGA using pre-defined dual-Vdd/ dual-Vt fabrics[C]// Proc ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FP- GA) Monterey, CA, USA: ACM, 2004:42-50.
  • 6Lin Y. Power modeling and architecture evaluation for FPGA with novel circuits for Vdd prograrnmability[C]// Proc ACM International Symposium on Field-Pro- grammable Gate Arrays ( FPGA ) Monterey, CA, USA:ACM, 2005.
  • 7Hou E S H. A genetic algorithm for multiprocessor scheduling[M]. Transactions on Parallel and Distribu- ted Systems (TPDS), 1994,5 (2): 113-120.

同被引文献27

引证文献4

二级引证文献6

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部