DDR2 SDRAM控制器接口的FPGA设计及实现

Design and Implementation of DDR2 SDRAM Controller Interface on FPGA

DDR2 SDRAM是第二代双倍数据传输速率同步动态随机存储器,以其大容量、高速率和良好的兼容性得到了广泛应用;DDR2芯片的控制较为复杂,为了解决DDR2芯片的驱动及功能验证问题,在介绍了其特点和工作机制的基础上,提出了一种简化的工作流程图,进而给出该控制器的总体设计、FPGA器件的引脚分配及验证方法;其中验证方法采用Verilog HDL,硬件描述语言构建了DDR2控制器IP软核的测试平台,通过ModelSim软件对DDR2仿真模型测试无误后,再使用QuartusII软件的嵌入式逻辑分析仪工具SignalTap II抓取FPGA开发板实时信号;开发板上的验证结果表明:DDR2芯片初始化成功;其引脚上有稳定的读写数据;在双沿时钟频率200 MHz下,写入数据和读出数据一致。故DDR2控制器设计达到要求,且控制器接口简单、工作稳定、移植性强。

DDR2 SDRAM, as the second generation dynamic random memory, is applied widely because of its large capacity, high speed and good compatibility. Because the control of DDR2 chip is more complex, a simplified work flow chart based on its characteristics and working mechanism is proposed to solve the problem of chip driver and/unction verification for DDR2. Furthermore, the overall design, ver- ification method and pin assignment of DDR2.controller in FPGA device are given. A test platform of the DDR2 controller IP core is built u- sing Verilog HDL language in the verification method, which test successfully the simulation model of DDR2 by Modelsim software. And then the real--time signals in FPGA evaluation board are captured by adopting SignalTapII Logic Analyzer embedded in QuartusⅡ software. The verification results in evaluation board show that the initialization of DDR2 chip is successful; pins of DDR2 chip have stable read and write data; the write data and read data are consistent under the dual edges clock with 200 MHz frequency. Therefore, the DDR2 controller meets design requirements, and it has simple interface, better stability and transplantablity.