基于FPGA的DDR3 SDRAM控制器设计及实现

Design and implementation of DDR3 SDRAM controller based on FPGA

文章基于Verilog语言设计并实现了一款基于高云FPGA芯片的DDR3 SDRAM控制器系统。本设计以GW2A55作为核心,参照JESD79-3F工业标准定义的DDR3 SDRAM时序操作、状态转换、接口定义等规范,实现了控制器的设计。设计主要分为控制层和物理传输层两个逻辑层级。通过综合验证本设计数据传输接口的速率可达到800Mhz,高负载运行下错误数据校准率为100%,芯片逻辑资源占用率低于6.5%,因此能够满足用户对高速数据传输以及可靠性和低资源占用的要求,同时具备同家族芯片可移植性强的优势,并给出了系统功能仿真的验证结果。

Using Verilog -HDL, Design and Implementation of DDR3 SDRAM Controller Based on Gowin FPGA, development Board useing GW2A55 as the core chip of the design. Refersto JESD79-3F Industry Standard which definition DDR3 SDRAM Operation Timing, finally Implementing the design.The design,data rate 800Mhz,calibration rate 100%,occupancy rate 6.5%,can meet the requirement of high-speed data transmission, system reliability, low resource utilization, high portability, at last given the waveform result of simulation.