用于电荷域流水线ADC的1.5位子级电路

1.5bit substage circuit for charge domain pipelined ADCs

针对高速高精度模数转换器的性能依赖于高增益带宽积运放而导致较大功耗的问题,提出了一种基于斗链式电荷器件的电荷域流水线1.5位子级电路.该子级电路使用增强型电荷传输电路来实现电荷传输和余量电荷计算,去除了传统流水线模数转换器中的高性能运放,可大大降低模数转换器的功耗.基于所提出的1.5位子级电路,在0.18μm CMOS工艺条件下,设计了一款10位、250MS/s电荷域流水线模数转换器.测试结果表明,该模数转换器样片在全速采样时对于9.9MHz正弦输入信号转换得到的无杂散动态范围为644dB,信噪失真比为56.9dB,而功耗为45mW.

A 1.5 bit sub-stage circuit based on bucket-brigade devices （BBD） for high speed charge domain pipelined ADCs is presented to solve the problem that the performances of high-speed, high-resolution ADCs rely on the opamps with large gain-bandwidth production, which results in large power consumption. Charge transfer and residue charge calculation are realized with a boosted charge transfer （BCT） circuit in the proposed 1.5 bit sub-stage, and therefore, the high-performance opamps in traditional pipelined ADCs are eliminated and the power consumption can be reduced remarkably. Based on the proposed 1.5 bit substage circuit, a 10 bit 250 MS/s charge domain pipelined ADC is designed in 0.18μm CMOS technology. Measurement results under a sampling frequency of 250 MHz and an input sinusoidal frequency of 9. 9 MHz show that the ADC achieves a spurious free dynamic range （SFDR） of 64.4 dE and a signal-to-noise-and- distortion ration（SNDR） of 56.9 dB, with power consumption of only 45 mW.