期刊文献+

一种静态单通道通讯模式异步流水线缓冲器

Study on A Single-Track Protocol Asynchronous Pipeline Buffer
下载PDF
导出
摘要 这是一种单通道两相静态异步流水线缓冲器电路,电路设计基于1-of-N握手协议进行通讯,不需等待应答信号即可完成数据传输。这是一种双轨缓冲器,设计时折中考虑了性能和面积的关系,采用了多米诺逻辑电路的实现方式,提高了面积利用率并且有很好的时序特性。基于TSMC 0.18μm CMOS工艺对电路功能和性能进行仿真测试,10级串连情况下最大吞吐量为2.65GHz/sec,电路向前传输延迟很低为116 ps,优于传统的STFB(single-track full-buffer)电路和GasP电路。仿真结果表明此方案适用于中高性能的异步电路设计。 This paper proposes a single track two phase static asynchronous Pipeline buffer, circuit design based on the 1-of-N handshake protocol to communicate, the circuit can complete data transmissions properly without acknowledgement signals, It is a kind of dual-rail buffer and provides a tradeoff between area and performance, using domino logic, effectively improve the utilization rate of the area and has very good latency characteristics. Simulations are made based on TSMC 0.18 μm CMOS technology, the results present that the circuit can work up to 2.65GHz under ten stages in series, and the forward transmission delay is very low for 116 ps circuit, superior to the STFB(single-track full-buffer) and GasP and circuit, the results presents that the circuit suitable for medium- to high-performance asynchronous circuit design.
出处 《集成电路应用》 2016年第12期52-56,共5页 Application of IC
基金 国家自然科学基金资助项目(61370153)
关键词 异步电路 1-of-N握手协议 单通道 异步流水线 集成电路 asynchronous circuit, 1-of-N handshake protocol, single track, asynchronousPipeline integrated circuit
  • 相关文献

参考文献2

二级参考文献16

  • 1周端,徐阳扬,曾平.异步系统的信号传送研究[J].固体电子学研究与进展,2006,26(1):120-123. 被引量:3
  • 2Tiwari V, Singh D, Rajgopal S, et al. Reducing power in high-performance microprocessors [A]. Proc. 35^th Ann. Conf. on Design Automation [C]. 1998. 732-737.
  • 3D Chapiro. Globally-Asynchronous Locally-Synchronous Systems [D]. Ph.D, thesis, Stanford University, 1984-10.
  • 4M Krstic, E Grass, F K Gurkaynak, P Vivet. Globally Asynchronous, Locally Synchronous Circuit: Overview and Outlook [J]. IEEE Design & Test of Computers, 2007, 24(5): 430-441.
  • 5Teehan Paul, Greenstreet Mark, Lemieux Guy. A survey and taxonomy of GALS design styles [J]. IEEE Design and Test of Computers, 2007, 24(5): 418-428.
  • 6Martin Alain I, Nystrom Mika. Asynchronous techniques for system-on-chip design [A]. Proceedings of the IEEE [C]. 2006, 94(6): 1089-1120.
  • 7Sutherland J, Fairbanks S, GasP: A minimal FIFO control [A]. Seventh International Symposium on Asynchronous Circuits and Systems. IEEE [C]. 2001.46-53.
  • 8Ferretti M, Beerel P A. Single-track asynchronous pipeline templates using 1-of-N encoding [A]. Design, Automation and Test in Europe Conference and Exhibition. IEEE [C], 2002. 1008-1015.
  • 9Ken Meekins, Dennis Ferguson, Moheb Basta, Delay Insensitive NCL Reconfigurable Logic [A]. Aerospace Conference Proceedings, IEEE [C]. 2002, 4(4): 1961-1966.
  • 10K M Fant, S A Brandt. NULL Convention Logic: A Complete and Consistent Logic for Asynchronous Digital Circuit Synthesis [A]. International Conference on Application Specific Systems, Architectures, and Processors [C]. 1996. 261-273.

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部