等波纹线性相位FIR滤波器设计与实现

Design and Realization of FIR Digital Filter with Equal-ripple Linear Phase

论文详细地阐述了等波纹线性相位FIR滤波器的一种设计和实现方法。首先,介绍了FIR滤波器的基本概念和等波纹线性相位FIR滤波器的优点,并且提出了用改进的分布式算法来实现滤波器中的乘累加运算。然后,利用Matlab得到一个具体指标的FIR滤波器的系数,并对系数进行了量化处理,以满足FPAG运算的要求。在滤波器的硬件设计上,先划分了各个功能模块,并给出了各个模块的实现方法。然后在XILINX的FPGA上用VERILOG硬件描述语言完成设计,并对滤波后的数据进行验证。验证结果表明:此方法节约了FPGA硬件资源的消耗,提高了数字信号处理的速度,所设计的滤波器满足系统的性能,达到了很好的滤波效果。

A design method of FIR digittl filter with equal-ripple linear phase is fully presented. The thesis firstly in-troduces the basic concept of FIR filter and advantages of FIR filter with equal-ripple linear phase and the improved distribu-ted algorithm is proposed to calculate multiply- accumulate. Then a specific FIR filter is designed using Matlab.In order to realize the filter with FPGA with device successfully, its coefficients are well handled quantitatively. In hardware design,the function of each module is divided firstly and the realization method of each module is also given .Then VERILOG hardware description language is used to complete the design . T h e filtering data shows that the proposed design method saves the re-sources in FPGA greatly and the designed filter operates correctly and realizes the function of high speed filtering.