高速峰值检测模块设计

Design of high speed peak detection module

针对一组32行20列的640个16位有符号随机二进制阵列数据设计峰值检测模块,数据采用串行输入,要求快速找到其中5个最大的峰值。峰值的定义是该数的绝对值大于它周围的8个数的绝对值。为了在最短的时间内在该串行随机数阵列中找到最大的5个峰值,模块采用一次扫描方式实现,这样的设计符合设计要求也能够得到最短检测用时,依据峰值定义设计扫描方式采用蛇形结构,通过把数据与前5个相关的数据比较,再与后5个相关的数据比较,接着与左边或右边相关数据比较,最后与之前确定的5个较大的峰值比较,来确定最新的5个较大的峰值的分步骤比较的思路。该模块采用FPGA(Altera CycloneⅡEP2C35F672C6)设计,利用Verilog HDL描述,整体消耗3214个逻辑单元。通过设定640个随机二进制数,对模块进行功能仿真和时序仿真。时序仿真结果表明,该模块可以工作在90Mhz时钟下,通过一次性扫描,工作大约7.15us完成对阵列的检测,输出5个最大的峰值的地址。

In order to quickly find the five largest peaks, -defined-as the absolute value of the number being the greatest among the absolute value of eight numbers around it, in the 640 16-bit signed random binary number array of 32 rows and 20 columns, we design a High-speed peak detection module. One-time scan is used in finding the maximum of five peaks in the array of random numbers to achieve time reduction of detection. Besides, we adopt a scan way of serpentine, in which the present data is compared with the first five related data, then the data after them, and followed by the left or right side of them. and finally the former five peak data, to determine the latest five larger peak. The module uses hardware programming language in FPGA （Altera Cyclone Ⅱ EP2C35F672C6） design. The module is simulated in timing and function through the 640 random binary numbers. The result of timing simulation shows that it takes about 7.15us to complete the detection of the array and output the five largest peak address work by using one-time scan undcr a frequency of 90Mhz.