一种基于MDAC优化的低功耗流水线A/D转换器

A low power pipelined ADC with improved MDAC

设计了一种低功耗16位100 MS/s的流水线A/D转换器。通过采用级间电容缩减技术,并优化增益数模转换器(MDAC)的结构,降低采样电容的面积。流水线前两级采用高性能低功耗运算跨导放大器(OTA),通过动态偏置技术进一步降低功耗。芯片采用0.18μm混合信号CMOS工艺,1.8 V单电源供电。经测试,流水线A/D转换器在5 MHz的输入频率下,信噪失真比(SNDR)为74.2 dB,无杂散动态范围(SFDR)为91.9 dB,整体功耗为210 mW。

The design of a low power 16-bit 100 MS/s pipelined analog-to-digital converter（ADC） is presented in this paper. The area of sampling capacitor and the chip is reduced by adopting stage scaling technology and optimizing the structure of multiply dig- ital-to-analog converter（MDAC）. Low power dissipation and high performance operational trans-conductance amplifiers（OTA） in the first two pipelined stages are realized by using dynamic biasing technology. This work is implemented in 0.18μm mixture signal CMOS process with a 1.8 V power supply. The pipelined ADC exhibits 91.9 dB SFDR and 74.2 dB SNDR, consuming 210 mW with 5 MHz differential input signal.