AXI4总线的USB2.0设备控制器IP核设计

USB2.0 Device Controller IP Core Based on AXI4 Bus

本设计依托星核计划——山东国产IP软核平台,基于最新片上总线AMBA4.0协议,使用VerilogHDL语言完成了主要由AXI4总线接口、ULPI模式控制、封包、解包和协议处理等模块组成的USB2.0设备控制器的IP核设计,通过综合验证证明了设计的正确性,并有效降低了FPGA逻辑资源占用率。可以根据实际应用要求将设计的USB2.0控制器IP核直接移植到FPGA内部,实现USB数据传输协议,省去了USB协议芯片,节省了产品开发成本,并且有效缩短了产品设计周期。

The design relies on the star nuclear program-Shandong domestic IP soft core platform. Based on the lastest on-chip bus AM- BA4.0 protocol, the design of USB2.0 device controller IP core is completed using Verilog hardware description language, which includes the AX14 bus interface module, the ULPI mode control module, the packet and unpacked module, the protocol processing module. The experiment results prove the correctness of the design, and it effectively reduces the logic resource utilization of FPGA. According to the actual application requirements, the designed USB2.0 controller IP core will be directly plant into the FPGA internal. It implementates the protocol of USB data transmission without the USB protocol chip. The design saves the product development cost and shorts the product design cycle effectively.