LDMOS工艺改进提高击穿电压的稳定性

Change Process to Improve the Stability of Breakdown in LDMOS

LDMOS(横向扩散金属氧化物半导体)由于可以承受一定的高电压、同常规CMOS平台容易兼容等特点,集成生产出的芯片兼备了耐压、低能耗、低成本等特性,在电源管理等领域得到了广泛的推广和应用。击穿电压和导通状态下单位面积的阻值是衡量LDMOS优良与否的关键参数,而在生产过程中,由于工艺步骤的波动,将会导致击穿电压等电性参数的波动。这是以40V N型LDMOS为例,研究了在实际生产中击穿电压的不稳定性,通过分析和实验,调整了生产工艺的顺序、具体工艺的条件,改善了击穿电压的不稳定性,使得击穿电压的标准差从工艺改进前的4 V降低到了改进后的1 V以内;由于击穿电压的稳定,我们缩小了器件布局的参数,从而降低了单位面积的导通电阻。

LDMOS （laterally diffused metal oxide semiconductor） has been widely promoted and applied in the field of power management etc.due to the its advantages. It can bear certain high voltage, easy to integrate with the conventional CMOS platform. The breakdown voltage and on state resistance of unit area is a measure of LDMOS quality. In production phase, there are many process steps which have variation. This will lead to the fluctuation of breakdown voltage and other electrical parameters. In this paper, we take 40 volt N LDMOS as an example, studied the process impact on the breakdown voltage. Through analysis and experiment, we changed the process sequence and specific process conditions, the breakdown voltage standard deviation has been improved from 4 volts to less than 1 volt. Due to this improved breakdown voltage stability, we have shrunk the layout parameters of our LDMOS, thereby reducing the unit area resistance.