20GSa/s高速采集模块设计与实现

Design and Implementation of 20GSa/s High-speed Data Acquisition Module

现代电子信号测试带宽已超过吉赫兹,对采样率达几十吉赫兹的高速数据采集与存储提出更高的要求,而现有的模拟数字转换(ADC)芯片只有几个吉赫兹的采集速率,不能直接满足对于超高采样速率的需求;文中提出了基于多片ADC并行交叉采样的20GSa/s高速采集与存储的设计方案,重点介绍了20GSa/s高速交叉采样的实现方式及误差来源和误差校准、交叉采样需要高速时钟的相位校准设计及具体校准方式、不同时钟域下160Gbps高速采集数据存储等核心技术,利用现有的高速ADC,最终实现了高达20GSa/s的数据采集与实时存储。

Testing bandwidth of modern electronic signal has exceeded gigahertz, so the rate of high-speed data acquisition and storage put forward higher requirements. The existing analog to digital conversion （ADC） has only a few gigahertz acquisition rate and cannot meet the requirement of ultra high-speed sampling data acquisition module. The paper uses multi chip ADCs and breaks through a series of key techniques, such as alternating time sampling, clock phase calibration, high speed storage, etc. By using the existing high speed ADC, the data acquisition and real-time storage of up to 20GSa/s are realized.