基于FPGA可配置任意整数半整数50%占空比时钟分频的实现

Design of FPGA-Based Frequency Dividing Circuit Capable of 50% Duty-Cycle Configuration for Integers/Half-Integers

基于FPGA,采用FPGA内部相移时钟,设计了一种可配置任意整数半整数50%占空比的时钟分频电路。以环形触发器电路为主要分频电路,根据各相移时钟的相位关系调整输出时钟占空比。设计结合时钟的相位关系与分频时钟周期的关键点,以多输入差分锁存结构完成输出时钟的占空比调整,最终实现整数、半整数分频。最后对电路进行了仿真验证。

In the paper, an FPGA-based frequency dividing circuit is designed. In the design, the FPGA phase-shift clock and flip-flop circuit are used to adjust the duty cycle of clock according to phase relation among phase-shift clocks. The design uses multi-input differential clock latch to achieve the integer/half-integer clock division. And the results are verified by simulations.