摘要
基于FPGA,采用FPGA内部相移时钟,设计了一种可配置任意整数半整数50%占空比的时钟分频电路。以环形触发器电路为主要分频电路,根据各相移时钟的相位关系调整输出时钟占空比。设计结合时钟的相位关系与分频时钟周期的关键点,以多输入差分锁存结构完成输出时钟的占空比调整,最终实现整数、半整数分频。最后对电路进行了仿真验证。
In the paper, an FPGA-based frequency dividing circuit is designed. In the design, the FPGA phase-shift clock and flip-flop circuit are used to adjust the duty cycle of clock according to phase relation among phase-shift clocks. The design uses multi-input differential clock latch to achieve the integer/half-integer clock division. And the results are verified by simulations.
作者
王兴宏
涂波
闫华
张艳飞
WANG Xinghong TU Bo YAN Hua ZHANG YanfeP(China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214072, China East Technologies, inc. Wuxi 214072, China)
出处
《电子与封装》
2017年第1期32-34,共3页
Electronics & Packaging
关键词
FPGA
占空比
整数半整数分频
差分
FPGA
duty-cycle
integer or half-integer frequency division
differential circuit