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基于SABL的防御差分功耗分析移位寄存器设计 被引量:1

Design of resistant differential power analysis shift register based on SABL
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摘要 通过对传统移位寄存器原理和灵敏放大型逻辑(Sense Amplifier Based Logic,SABL)电路的研究,提出一种能够防御差分功耗分析的移位寄存器设计方案。该方案首先采用主从触发的方式,设计基于SABL电路的清零置位D触发器;然后利用该触发器与SABL逻辑门实现多位移位寄存器电路。Spectre仿真验证表明,所设计的移位寄存器逻辑功能正确,在多种PVT组合下NED均低于2.66%、NSD均低于0.63%,具有显著的防御差分功耗分析性能。 By researching on the principle of traditional shift register and Sense Amplifier Based Logic (SABL) circuit, a scheme of resistant differential power analysis shift register is proposed. Firstly, the proposed shift register circuit implements the clear set D flip-flop with the master-slave trigger mode based on SABL circuit. The D flip-flop and SABL logic gates are integrated to design a multi-bits shift register circuit. Spectre simulation results show that the circuit of shift register has correct logic function. Under testing of PVT combinations, NED and NSD of are lower than 2.66% and 0.63%, respectively. It is shows that the proposed shift register has significant performance in resistant differential power analysis.
出处 《电子技术应用》 北大核心 2017年第2期40-43,共4页 Application of Electronic Technique
基金 国家自然科学基金(61274132 61474068) 浙江省自然科学基金(LQ14F040001)
关键词 SABL 防御差分功耗分析 移位寄存器 信息安全 SABL resistant differential power analysis shift register information security
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  • 1阎石.数字电子技术基础[M].北京:高等教育出版社,2008.
  • 2Tri K, Verbauwhede I. A Digital Design Flow for SeCure Integrated Circuits [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(7): 1197-1208.
  • 3Wu K, Li H, Yu F. Retrieving Lost Efficiency of Scalar Multiplications for Resisting against Side-Channel Attacks [J]. Journal of computers, 20t0, 5(12): 1878-1884.
  • 4Alioto M, Poli M, Rocchi S. A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(5): 711-724.
  • 5Ctani R E, Mirzakuchaki S, Atani S E, et al. On DPA-resistive Implementation of FSR-based Stream Ciphers Using SABL logic Styles [J]. International Journal of Computers, Communications and Control, 2008, 3(4): 324-335.
  • 6Stefan Mangard, Elisabeth Oswald, Thomas Popp. Power Analysis Attacks: Revealing the Secrets of Smart Cards [M]. Austria: Springer, Graz University of Technology, 2007. 119-158.
  • 7Guilley S, Sauvage L, Flament F, et al. Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics [J]. IEEE Transactions on Computers, 2010, 59(9): 1250-1263.
  • 8Marco Bucci, Luca Giancane, Raimondo Luzzi et al. Three-Phase Dual-Rail Pre-Charge Logic [A]. 8th International Workshop on Cryptographie Hardware and Embedded Systems (CHES) [C]. 2006. 232-241.
  • 9Menendez E, Mai K. A Comparison of Power-Analysis-Resistant Digital Circuits [A]. IEEE International Symposium on Hardware-Oriented Security and Trust [C]. 2010.64-69.
  • 10Rabaey Jan M, Anantha Chandrakasan, Borivoje Nikolic. 周润德等.数字集成电路一电路、系统与设计[M].北京:电子工业出版社,2004.62-81.

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