摘要
提出了一种高电源纹波抑制比的低压差线性稳压器.该低压差线性稳压器通过提高带隙基准的电源抑制比以达到提高LDO(低压差线性稳压器)低频电源纹波抑制的能力.在TSMC 0.18μm CMOS工艺下进行了仿真验证,仿真结果表明,该LDO最大负载电流可以达到80mA,当负载电流在0~80mA范围内变化时,开环相位裕度均大于64°,证明了低压差线性稳压器的高稳定性.当负载电流从0mA跳变到80mA时,系统的输出电压过冲仅为15mV,环路响应时间仅为0.5μs.当负载电流为80mA,测得10kHz时的电源纹波抑制比为-60.82dB,100kHz时LDO的电源纹波抑制比为-57.66dB.
An improved power supply ripple rejection （PSRR） low drop-out （LDO） voltage regulator circuit is proposed. The LDO improves the ability of power supply ripple rejection ratio by improving power supply rejection ratio of the handgap reference. This approach is tested in TSMC 0. 18 μm COMS process. The results show that the maximum load current is 80 mA, and the open-loop phase margin is not less than 64° at a load current from 0 to 80 mA which proves the high stability of LDO. In addition, the circuit achieves a transient response with 15 mV voltage variation and 0. 5 gs settling time for an 80 mA load step. The PSRR at 10 kHz is -60. 82 dig and 100kHz is 57. 66 dB.
出处
《微电子学与计算机》
CSCD
北大核心
2017年第2期58-62,共5页
Microelectronics & Computer
