摘要
Multisim仿真软件是电路分析和设计中常用的一种辅助手段,但若时序逻辑电路设计不当,因时延造成信号畸变,引发电路输出状态偏离原有的"轨道",将使得电路功能无法实现。因此,竞争冒险是时序电路设计中必须考虑的重要方面,加入复位电路设计,是解决时序逻辑电路测试生成问题的有效方法。
Circuit simulation is a common auxiliary analysis and de- sign means by Multisim software, but if the sequential logic circuit design is not correct, the signal distortion may be caused by time delay, and then the output state will deviate from its original orbit, what makes the circuit functions cannot be achieved. So the race and hazard is quite essential and must be considered when designing logic circuit. Sometimes adding reset circuit design is an important method of sol- ving the sequential logic circuit test generation problem.
作者
胡洁微
周宦银
胥飞燕
李丽蓉
单坤
HU Jiewei ZHOU Huanyin XU Feiyan LI Lirong SHAN Kun
出处
《中国教育技术装备》
2016年第24期23-25,共3页
China Educational Technology & Equipment