摘要
针对N+掺杂区设计了一种提高单位面积电流密度的VDMOS器件结构,新结构中源极N+掺杂区为梯形结构。该结构减小了元胞的尺寸,提高了单位面积的元胞数量,从而提高了单位面积的电流密度,减小了VDMOS器件的封装尺寸。
This paper designed a structure of VDMOS device＇s N＋ doping area,which using a improved the current density per unit, the source N＋doping area is the trapezoidal structure.This problem,this paper designed a kind of improving current density per unit area of VDMOS device structure,the new structure of the source N type doping area to the trapezoidal structure. This structure,reduce the size of the cell,improve the cell number per unit area,so as to improve the current density per unit area,and decrease the size of the VD- MOS device packaging.
出处
《黑龙江科技信息》
2016年第22期204-204,共1页
Heilongjiang Science and Technology Information
