一种可应用于高速卫星通信的FPGA时钟改进方案

Modified FPGA clock scheme for high-speed satellite communication

随着通信技术的发展,卫星通信朝着实时化、数字化和宽带化方向发展。然而,在卫星产品设计中,传输速率越高,通常所需要的时钟频率越高,对宇航器件选型、时钟信号传输、高频电磁干扰、PCB走线设计的要求也更高。在高速通信系统中,时钟质量是决定系统性能指标的关键因素。因此,合理的时钟设计方案尤为重要。因此,提出一种改进的FPGA时钟处理方案。该方案不仅大幅降低了时钟频率,而且软硬件设计简化,降低了成本。经测试验证表明,该时钟改进方案可应用于高速卫星通信系统。

With the development of communication technology, satellite communication guickly moves toward the direction of real-time, digital and broadband. However, in the design of satellite products, the higher the transmission rate, the higher the needed FPGA clock frequency is, and then the reguirement for selection of space device, transmission of clock signal, high frequency electromagnetic interference, design of PCB also becomes even higher. In the high speed communication system, the clock quality is the key factor for determination of the system performance. In this paper, a modified FPGA clock processing scheme is proposed, which could not only reduce the clock frequency and product cost, but also simplify the software and hardware design. The experiment result shows that the proposed scheme could be applied to the high speed satellite communication system.