一种采用双层仲裁机制的新型总线仲裁器

Novel bus arbiter with the two-level arbitration mechanism

随着系统芯片复杂度的持续提升,不断增加的带宽需求和不可预测的线延迟使总线逐步成为提高系统芯片性能的瓶颈.总线仲裁器对系统芯片的性能起决定作用,所以对高效仲裁器的研究具有重要意义.鉴于仲裁器赋权的决策由不依赖硬件结构的仲裁算法确定,所以创建了一种验证仲裁器性能的软件仿真平台,并利用该仿真平台设计了一种基于双层仲裁器结构和层间判断的新型仲裁器.仿真结果表明,新型仲裁器实际赋权的比例与目的带宽比之间的均方差比两款传统仲裁器的分别降低了54.4%和50.8%,实现了赋权比例与目的带宽比的逼近.

With the continuous increase in the complexity of the System-on-Chip （SoC）, the growing demand for bandwidth and the unpredictable wire delay have made buses the bottleneck of SoC properties; researches on efficient bus arbiters, which play a decisive role in the properties of SoC, are of great significance. In view of the decisions made by arbiters are determined by arbitration algorithms which have little reliance on hardware structures, a software simulation platform is provided in this paper to verify the properties of arbiters, on which a novel arbiter based on the structure and trans-level judgment of the two- level arbiter is proposed. Simulation results show that the novel arbiter would reduce the standard deviation between the actual granted ratio and the required bandwidth ratio by 54.4% and 50.8% respectively in comparison with two traditional arbiters, indicating the approximation between granted ratio and the required bandwidth ratio.