基于时钟的数字电路可重构BIST设计研究

BIST Design Reconfigurable Digital Circuit Based on Test-per-clock

研究了基于时钟的数字电路可重构内建自测试(BIST)设计。BIST不通过ATE设备加载测试矢量和检测测试响应,通过内置激励电路和响应分析电路来实现。在很大程度上降低了对ATE带宽的要求。当前电路集成度高,整体测试时可观察性和可控制性不理想,测试效果不佳,因此将大规模数字电路进行划分测试,通过基于时钟的可重构BIST设计,减少电路的测试矢量数,进而减小测试功耗。通过对可重构BIST各模块进行仿真和故障模拟验证,验证了设计的可行性。

Reconfigurable digital circuit based on test-per-clock was studied. BIST did not load test vectors and test equip- ment test response by ATE, through built-in excitation circui try and response analysis circuit. The bandwidth requirements of ATE was reduced largely. The current circuit was highly integrated, while the overall test observability and controllability were not satisfactory, and test results were not good, so the large-scale digital circuit test was divided by the number of clock reconfig- urable BIST design to reduce circuit test vectors, thereby reducing test power. By reconfignrable modules BIST simulation and fault simulation and verification, the feasibility of the design was verified.