一种10位10MS/s自补偿SAR A/D转换器

A 10-bit 10MS/s Self-Compensation SAR Analog-to-Digital Converter

基于SMIC 0.18μm CMOS工艺,设计了一种10位自补偿逐次逼近(SAR)A/D转换器芯片。采用5+5分段式结构,将电容阵列分成高5位和低5位;采用额外添加补偿电容的方法,对电容阵列进行补偿,以提高电容之间的匹配。采用线性开关,以提高采样速率,降低功耗。版图布局中,使用了一种匹配性能较好的电容阵列,以提高整体芯片的对称性,降低寄生参数的影响。在输入信号频率为0.956 2MHz,时钟频率为125MHz的条件下进行后仿真,该A/D转换器的信号噪声失真比(SNDR)为61.230 8dB,无杂散动态范围(SFDR)达到75.220 4dB,有效位数(ENOB)达到9.87位。

Based on SMIC 0.18μm CMOS process, a 10-bit self-compensation successive approximation analog- to-digital converter was designed. The 5 ＋5 segment-capacitor-array structure was adopted with 5 MSB part and 5 LSB part of capacitor array. In order to improve the matching between capacitances, an extra compensating capacitor was used in the capacitor array. Linear switches were applied to enhance the sampling rate and to reduce the power consumption. To improve the symmetry of the whole chip and to reduce the effects of parasitic parameters, a well matching capacitor array was used in the whole chip layout. The post-simulation results showed that the SNDR of the ADC was 61. 230 8 dB, the SFDR was 75. 220 4 dB, and the ENOB was 9. 87 bit at 0. 956 2 MHz input signal frequency and 125 MHz sample clock frequency.