一种低抖动低杂散的亚采样锁相环

A Low Jitter Low Spur Sub-Sampling PLL

设计了一个5.156 25GHz低抖动、低杂散的亚采样锁相环,使用正交压控振荡器产生4路等相位间隔时钟。分析了电荷泵的杂散理论,使用差分缓冲器和互补开关对实现了低杂散。使用Dummy采样器和隔断缓冲器,进一步减小了压控振荡器对杂散的恶化。该亚采样锁相环在40nm CMOS工艺下实现,在1.1 V的供电电压下,功耗为7.55 mW;在156.25 MHz频偏处,杂散为-81.66dBc;亚采样锁相环输出时钟的相位噪声在10kHz^100 MHz区间内积分,得到均方根抖动为0.26ps。

A 5. 156 25 GHz low jitter low spur sub-sampling phase-locked loop（SSPLL） was presented. A QVCO was used to generate 4 space clocks with equal phases. The CP spur mechanisms were analyzed, and the spur effects were minimized by using differential buffers and complementary switch pairs. The VCO＇s sampling spur effect was also minimized by using dummy samplers and isolation buffers. The SSPLL was implemented in a standard 40 nm CMOS process. It consumed 7.55 mW from a 1.1 V supply. The reference spur could be as low as --81.66 dBc at 156.25 MHz offset. The phase noise of SSPLL＇s output clock was integrated from 10 kHz to 100 MHz, and the obtained output RMS jitter was 0.26 ps.