一种低压差CMOS线性稳压器的设计

Design of a CMOS Low-Dropout Regulator

设计了一种输入电压范围为1.9~5V,输出电压为1.8V的LDO。采用零点-极点追踪频率补偿方案,补偿结构简单,可动态补偿输出极点;利用PMOS管与NMOS管阈值电压相互补偿的特性,设计了基准电压源,具有结构简单、版图面积小等优点。基于GSMC 0.18μm CMOS工艺,采用Spectre软件对电路进行仿真。仿真结果表明,电路的带宽为4 MHz,低频段时电源抑制比达到125dB,静态电流只有80μA。

A LDO circuit with 1.8 V output voltage and varied input voltage from 1.9 V to 5 V was proposed. In the design of the circuit, zero-pole tracking frequency compensation scheme was adopted, which had simple structure and could dynamically compensate the output pole. A reference voltage source based on mutual compensation of threshold voltage of the PMOS and NMOS transistors was introduced, which had simple structure and small layout area. It was designed in the GSMC 0.18μm CMOS process and simulated by Spectre. The results revealed that the unity gain bandwidth was 4 MHz, the PSRR was 125 dB in low frequency bands and the quiescent current was only 80 μA.