深亚微米GGNMOS器件ESD鲁棒性的优化与模拟

Optimization Analysis and Modeling of ESD Robustness in Deep Submicron GGNMOS Technology

基于单指条栅接地N型场效应晶体管(GGNMOS)在静电放电(ESD)时的物理级建模方法,仿真分析了版图参数和工艺参数对器件ESD鲁棒性的影响。提出了一种可提高器件ESD保护性能的优化设计,即硅化扩散工艺下带有N阱的多指条GGNMOS结构。对单指条器件模型进行修正,得到的多指条模型能预估不同工艺条件下所需的N阱长度,以满足开启电压Vt1小于热击穿电压Vt2的设计规则。由仿真结果可知,对于一个0.35μm工艺下的10指条GGNMOS,通过减小栅极长度(L)、提高衬底掺杂浓度(N_(BC))和漏极掺杂浓度(N_E),以及从修正模型中得到合适的N阱长度,均可以增强器件的ESD鲁棒性。

Based on the physical-level models of single finger GGNMOS under ESD conditions, the effects of layout parameters and process parameters on the ESD robustness of the device were simulated and discussed. Moreover, an optimized design of silicided-diffusion multi-finger GGNMOS with the N-well was proposed, which could improve the protection capability of the device. The single finger device models was modified, and based on it, the modified models of multi-finger GGNMOS enabled the evaluation of N-well length to meet the design rule of Vtl〈Vt2, where Vt1 was the turn on voltage and Vt2 was the thermal breakdown voltage. The simulation results indicated that the ESD robustness could be enhanced by designing a 10-fingers GGNMOS under 0. 35 μm process with shorter gate length （L）, higher substrate doping concentration （NBc）, higher drain impurity concentration （NE） and appropriate value of N-well length derived from the advanced models.