Verilog到Java在线翻译器Verilog2Java的设计与实现

DESIGN AND REALIZATION OF VERILOG2JAVA ONLINE TRANSLATOR THAT TRANSLATES FROM VERILOG TO JAVA

为实现Verilog语言的跨平台操作,完成软硬件之间的协同设计验证,提出了在线翻译器Verilog2Java的设计思路。通过对Verilog和Java语言的比较,首先设计出一组从Verilog到Java的翻译规则,然后采用B/S结构,将已定义的规则加载到配置好的Eclipse工作环境下,再到数据库中执行相应的查询操作,最终生成功能等价的Java目标代码。结果表明:该翻译器经多次实例验证,可完成预期的设计功能。

A design thinking that translates from Verilog to Java is proposed to achieve cross-platform operation of Verilog language and complete collaborative design and verification between hardware and software. By comparing the similarities between Verilog and Java language,a set of conversion rules for the translation from Verilog to Java is designed. Then the B / S structure is adopted to load the defined rules to configure Eclipse working environment,and then execute the search operation in the database. Finally,a functional equivalent of the Java language is generated. The results show that the translator is able to complete the expected design function.