基于DDR3高速电路拓扑结构的优化与仿真

OPTIMIZATION AND SIMULATION OF HIGH-SPEED CIRCUIT TOPOLOGY BASED ON DDR3

以JEDEC公司所设计带寄存器内存条(RDIMM)B0公版DDR3的PCB为研究对象,并根据寄存器和内存条的IBIS仿真模型提取对应的时钟信号走线的Fly-By拓扑结构。通过SigXplorer软件对原先的Fly-By拓扑结构进行仿真并分析,然后,根据现有的拓扑结构特点设计出一种新的拓扑结构Fly-Shu。最后,通过反射仿真的矩形波形和串扰仿真的眼图波形与原先Fly-By拓扑结构仿真结果进行对比,发现新设计的Fly-Shu拓扑结构在高速电路中对于常见反射和串扰影响方面具有更强的抑制作用,从而保证了高速信号在传输过程中更高的完整性。同时,新设计出的Fly-Shu拓扑结构对以后的高速信号的PCB设计和仿真起到了很好的借鉴作用。

By studying the public version of DDR3 PCB which is designed by JEDEC company with register memory（RDIMM） B0,the corresponding Fly-By Topology of clock signal line is extracted according to the IBIS simulation model of RDIMM. Using SigXplorer software to simulate and analyze the original Fly-By Topology. Then,according to the existing topology features,a new topology called Fly-Shu is designed. In the end,comparing the rectangular waveform come from the reflected simulation and Eye waveform come from the crosstalk simulation with the simulation result of the original Fly-By Topology,it is found that the new designed Fly-Shu Topology is better at restraining the influence of reflection and crosstalk,so that the higher integrity of high speed signal integrity in transmission is ensured. At the mean time,the new design of the Fly-Shu Topology can offer a good reference in designing and simulating the PCB of high speed signal.