FPGA与ARM的GPMC总线通信接口设计

GPMC Bus Interface Based on FPGA&ARM

为满足数据快速、稳定的传输,同时简化硬件设计,增强设计的灵活性,本文提出了一种利用ARM自身带有的GPMC总线作为ARM与FPGA数据传输的接口方案,并详细介绍了GPMC接口原理及FPGA内部GPMC接口时序的实现。首先,FPGA内部要实现ARM处理器的GPMC接口的读写时序,从而完成ARM与FPGA的通信。其次,FPGA完成对高速信号的采集以及存储,当存储到一定量时,FPGA中断ARM处理器进行数据的读取。仿真结果表明,与以往接口相比,该接口能完成高速信号的稳定传输。

To meet the rapid and stable transmission of the data, simplify the hardware design and increase the flexibility,a scheme of u- sing GPMC＇s own ARM bus as the data transmission interface between ARM and FPGA is proposed. The principle of GPMC interface and the implementation of GPMC interface timing in FPGA are introduced in detail. Firstly,the internal FPGA achieves the reading and writing timing of the GPMC interface in ARM processor,then the design completes the communication between ARM and FPGA. Secondly, the FPGA finishes collecting and saving for the high-speed signal. When the stored data to a certain amount, the FPGA interrupts the ARM processor for data read. The simulation results show thatthe new interface can complete the high-speed signal transmission stability comparing with the previous interface.