基于FPGA的可调节FIR滤波器的设计与实现

Design of adjustable FIR filter based on FPGA

基于灵活自适应的空口波形技术F-OFDM(Filtered OFDM)是现代通信技术的研究热点,设计并实现可调FIR滤波器是实现该技术的核心工作之一。本文设计的基于FPGA的可调节FIR滤波器系数的自适应调整是通过控制算法对信道中的信号进行快速检测,然后将结果和滤波器的输出结果进行差值计算进行反馈调节。利用Quartus II和DSP Builder设计基于FPGA的16阶系数可调FIR滤波器,给出核心模块的设计电路图和仿真结果。仿真结果表明:基于灵活自适应空口波形技术可以在FPGA上实现,而且由于FPGA具有天然的并行性,实际的通信系统中可以采用并发模式进行,达到提高信号传送速率的目的。

F-OFDM is one of the key hotspots in modern communication system. Designing and instrumenting the adjustable FIR filter is cer- tainly part of F-OFDM. In this paper, we design an adjustable FIR filter based on FPGA, and its filter coefficients can vary with the running difference between the output of filter and the frequency of input signal. We design the filter based on the Quartus II and DSP builder provided by Ahera. The simulation results reveal that the techniques of F-OFDM can be instrumented on FPGA. In addition, since FPGA has its own a- bility of natural parallel computing, improving the running efficiency would come true on the FPGA.