一种应用于10位SAR ADC的高精度比较器电路设计

Designing a high precision comparator for 10-bit SAR ADC

提出一种应用于10位逐次逼近型模数转换器(SAR ADC)的高精度比较器,具有精度高、功耗低的特点。该比较器采用差分结构的前置放大电路,提高输入信号的精度,其自身隔离效果减小了锁存器的回踢噪声和失调电压。动态锁存电路采用两级正反馈,有效提高比较器的响应速度。输出缓冲级电路增强输出级的驱动能力,调整输出波形。该比较器电路采用SMIC 65 nm CMOS工艺技术实现,使用Cadence公司Spectre系列软件对进行仿真,设置工作电压2.5 V,采样频率2 MHz,仿真结果表明,比较器的分辨率是0.542 5 mV,精度达到11位,失调电压为1.405μV,静态功耗为63μW,已成功应用于10位SAR ADC。

A high precision comparator applied to a 10-bit successive approximation analog-to-digital converter （SAR ADC） is presented in this paper. It has the characteristics of high precision and low power dissipation. The differential structure of the preamplifier circuit improves the accuracy of the input signal, and its isolation effect reduces the effect of kickback noise and latch offset voltage. Two level dynamic latch circuit effectively improves the speed of eomparator. Output buffer circuit increases the drive ability of the output stage and adjusts the output wave- form. SMIC 65 nm CMOS process technology is used to realize the eomparator circuit. Cadence series software Spectre is used to design the cir- cuit simulation at the voltage supply of 2.5 V and sampling frequency of 2 MHz. The simulation results show that the resolution of the precision comparator is 0. 542 5 mV, accuracy is 11 bit, offset voltage is 1. 405 μV and static power dissipation is 63 μW.