基于FPGA的流水线单精度浮点数乘法器设计

A single precision floating-point multiplier design of assembly line based on FPGA

针对现有的采用Booth算法与华莱士(Wallace)树结构设计的浮点乘法器运算速度慢、布局布线复杂等问题,设计了基于FPGA的流水线精度浮点数乘法器。该乘法器采用规则的Vedic算法结构,解决了布局布线复杂的问题;使用超前进位加法器(Carry Look-ahead Adder,CLA)将部分积并行相加,以减少路径延迟;并通过优化的4级流水线结构处理,在Xilinx~ISE 14.7软件开发平台上通过了编译、综合及仿真验证。结果证明,在相同的硬件条件下,本文所设计的浮点乘法器与基4-Booth算法浮点乘法器消耗时钟数的比值约为两者消耗硬件资源比值的1.56倍。

Considering the existing floating-point multiplier based on Booth algorithm and Wallace tree, which has slow speed and complex lay- out, a single precision floating-point multiplier is designed using Vedic mathematics. The Vcdic multiplier（VM） has a regular structure there- fore can be easily placed and routd in a silicon chip. Carry look-ahead adder （CLA） structure is used to add the part of the product in parallel for reducing the path delay. The floating-point multiplier design employs an optimized 4-stage pipeline processing and the simulation and syn- thesis are done in Xilinx ISE 14.7. The results prove that under the condition of the same hardware, the ratio of consumed clock number be- tween the designed multiplier in this paper and arithmetic point multiplier based on 4-Booth is about 1.56 times than that of consumed hardware