数字下变频DDC的设计与FPGA实现

Design of Digital Down Conversion and FPGA implementation

本文以提高软件无线电中DSP的运算速度为目的,设计了高效的数字下变频系统,在得到有效信息的同时可以节省大量的运算、存储空间。本方案是基于FPGA设计的,详细介绍了数字下变频的各种滤波器的设计,包括CIC滤波器、HB滤波器、FIR滤波器,并编写verilog HDL程序实现各个模块,最后在FPGA中验证了设计的有效性、可行性。

This article designs an efficient digital down conversion system, in order to improve the computing speed of DSP in software radio, which can save a lot of computing and storage space. This scheme is based on the design of FPGA, introduced the design of digital down conversion filter in detail, including CIC filter, HB filter, FIR filter. In the end, we carries out the design of the DDC and verified its feasibility.