一种交织汉明码编译码器设计及其FPGA实现

Design of interleaved hamming code'sencoder and decoder and FPGA implementation

随着信号传输速度的提高,高速信号抗干扰能力也越来越低,人们对信号可靠性有了更高的要求。为了抵抗高速信号在传输过程中因为各种干扰而产生误码,人们提出了纠错编码理论。其中汉明码是最早提出的一类纠错编码,具有译码电路简单,译码延时小的优点,但是其只能纠正一位随机错误。为了提高汉明码的纠错能力,结合其译码优点,利用交织的方式设计了一种交织汉明码。根据循环汉明码的生成多项式,设计了并行输出的汉明码编码器和具有双译码电路的译码器,并利用移位寄存器设计了交织器和解交织器,构成了交织汉明码编译码电路。基于FPGA实现该交织汉明码编译码器,行为仿真结果表明,该交织汉明码大大提高了汉明码的纠错能力。

With the improvement of signal transmission speed,the high-speed signal＇s anti-interference ability is becoming lower and lower,and higher demandof the signal reliability is necessary.In order to reinforce the high-speed and protect the process of transmission from disturbing,the theory of error-correcting codes was put forward.Among various kinds of error correction coding,the hamming code is the earlist to be discovered,it has a simple decoding circuit andshort decoding time delay,but can only correct single random error.In order to improve the hamming code＇s error correction ability and take advantages of its decodingbenefits,using interleaving to design a kind of interleaving hamming code.According to the cyclic hamming code generating polynomial,designed a parallel output hamming encoder and a double decode circuit decoder.At the same time the interlace encoder and decoder are designed baseed on shift register,constitutes the interleaving hamming encoder and decoder.Four input informations are encoded by four hamming encoders synchronously,then interlacing the four hamming codes.The interlwaving hamming decoder firstly deinterlace the receive information,and then correct the potential errors by hamming decoder.The design of the interleaving hamming code is implemented based on FPGA,and the simulation results show that the interleaving hamming code has greatly increased the hamming code error correction ability.