基于FPGA的DDR3控制器设计

Design of DDR3 controller based on FPGA

作为SDRAM的第3代动态同步存储器,DDR3以其高速率存储、大容量、低功耗以及良好的兼容性得到广泛应用。基于目前高速信号存储领域对存储性能要求越来越高,利用Virtex-7系列FPGA实现了DDR3控制器,自行设计用户接口模块有效控制数据读写。该DDR3控制器有效解决了目前存储器速率有限、功耗较大、带宽较低的问题。最终通过Modelsim仿真平台进行功能仿真验证,并且在硬件平台测试,验证了该控制器稳定性好,占用资源少以及可移植性强。

As the third generation SDRAM dynamic synchronous memory, DDR3 has been widely used for its high speed, large capacity, low power consumption and good compatibility. Because of the requirements of the current high speed signal storage area of storage performance becoming more and more high, this paper uses the Virtex-7 FPGA to achieve the DDR3 controller, designed the user interface module to effectively control the data read and write. The DDR3 memory controller is an effective solution to the current rate is limited, a larger power and low bandwidth problems. Finally, using the Modelsim simulation platform for functional simulation, and in the hardware platform test, the stability of the controller is good, the occupation of less resources and strong portability.