一种SRAM辅助新型非易失性缓存的磨损均衡方法

SRAM-Assisted Wear Leveling for Emerging Non-Volatile Caches

随着半导体工艺的发展,处理器集成的片上缓存越来越大,传统存储器面临着存储密度低和漏电功耗高等问题日益严峻.近年来,新型非易失性存储技术展现出漏电功耗低、存储密度高和可扩展性强等优点,是最有潜力构建大容量缓存的新技术.然而,非易失性存储器的写操作次数有限,作为缓存将限制其寿命.同时缓存上的写操作是不均匀的,存在缓存组间和组内的写波动,这一访问特点将导致缓存的每部分磨损不均衡,现有的缓存管理策略却不能感知缓存的写波动.为解决这一问题,提出了SRAM辅助新型非易失性缓存的磨损均衡(SRAM-assistEd weAr Leveling,SEAL)方法,该方法包含写波动感知的缓存块迁移算法(Write Variation-aware blOck Migration,WVOM)和阈值指导的缓存块迁移算法(Threshold gUided Block mIgration,TUBI).SEAL方法重点关注写波动大的缓存组和写强度高的缓存单元,着力减少这部分缓存单元的写压力.WVOM感知缓存组间写波动并迁移写强度大的缓存组,用于解决组间磨损均衡问题.TUBI迁移缓存组内写局部性高的缓存块来达到组内磨损均衡.实验结果表明,SEAL方法与基准配置相比,缓存的磨损程度平均减少了34.2%,缓存的平均寿命提升了175%,性能平均提高了0.735%,系统的动态功耗平均降低了5.65%.同时,SEAL方法与最新的研究成果相比,缓存的磨损程度平均减少了13.1%,缓存的平均寿命提升了20%.

With the development of semiconductor technology and complementary metal oxide semiconductor（CMOS）scaling,the size of on chip cache memory gradually increases in modern processor design.The storage cell density of traditional static random access memory（SRAM）is very low and SRAM has been close to the limit due to its physical property.Furthermore,SRAM consumes a large amount of leakage power which could severely affect the whole system performance.In recent years,the emerging non-volatile memory（NVM）has shown a lot of attractive features,such as low leakage power,high storage density and better scalability.The NVM based cache design has become one of the most promising candidates to build large on chip caches in themodern processor architecture.However,both of these NVMs suffer from high write latency and limited write endurance problems.The lifetime of on chip non-volatile caches will be constrained by these issues when we use NVM to architect the cache.What＇s more,the write operation on cache is unbalanced distribution in the cache set and there exist write variations among inter sets and intra sets.These cache access characteristics will lead to uneven wear for each cache storage cells.Unfortunately,the wear leveling approaches for NVM based main memories could not be simply used to NVM based on chip caches because main memories only have inter set variations.Meanwhile,most of the existing cache management policies are write variation unaware at present.This situation might result in unbalanced write traffic to every cache cells,which causing heavily written cells will fail much earlier than the others.To solve the write endurance problems,this paper proposes a novel technique named SRAM assistEd weAr Leveling（SEAL）for non-volatile caches to minimize both inter and intra set write variations.SEAL contains two algorithms：Write Variation-aware blOck Migration algorithm（WVOM）and Threshold gUided Block mIgration algorithm（TUBI）.The main idea of the SEAL scheme focuses on the high write variation cache set and the high write intensive cache storage cells.SEAL attempts to reduce the write pressure of these cache cells.The WVOM algorithm is used to improve inter set wear leveling by detecting the write variation of cache set and then migrating the blocks from write intensive cache sets to the SRAM.The TUBI algorithm aims to migrate the high write locality cache blocks in a cache set to achieve the intra set wear leveling.The experimental results show that,compared with the baseline,on average,the proposed scheme reduces the write variation by 34.2% and thereby improves the wear leveling effectively.In addition,the lifetime of on chip non-volatile caches is significantly improved by 175% and the performance is improved by 0.735%.Furthermore,the dynamic energy consumption of the system is also reduced by 5.65% on average.Meanwhile,The SEAL scheme is compared with the most recent related work.The proposed scheme reduces the write variation by 13.1% on average and the wear leveling is improved simultaneously.Moreover,the lifetime of on chip non-volatile caches is improved by 20% on average.