用于高速流水线ADC的低抖动多相时钟产生电路

Low-Jitter Multi-Phase Clock Generator for High Speed Pipelined ADC

设计了一种用于高速流水线ADC的多相时钟产生电路。通过采用一种高灵敏度差分时钟输入结构和时钟接收电路,降低了输入时钟的抖动。该多相时钟产生电路已成功应用于一种12位250MSPS流水线ADC,电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,面积为2.5 mm2。测试结果表明,该ADC在全速采样条件下对20 MHz输入信号的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,积分非线性误差(INL)为-0.4^+0.65 LSB,微分非线性误差(DNL)为-0.2^+0.15 LSB,功耗为320 m W。

A Low jitter multi-phase clock generator for high speed pipelined ADC is presented. In order to reject the clock jitter, the high sensitivity differential clock input structure and clock receiver is used. A 12-bit250 MSPS pipelined ADC based on the proposed sub-stage circuit is presented. The ADC is manufactured in0.18 μm 1P5 M 1.8 V CMOS process, with a die area of 2.5 mm^2. The test result shows that the ADC achieves an SNR of 69.92 d B, an SFDR of.81.17 d B, an INL of-0.4 to ＋0.65 LSB, a DNL of-0.2 to ＋0.15 LSB and a power consumption of 320 m W for 20 MHz input at full sampling speed.