0.18 μm CMOS器件SEL仿真和设计

Simulation and Design of SEL for 0.18 μm CMOS Devices

宇宙空间存在大量高能粒子,这些粒子会导致空间系统中的CMOS集成电路发生单粒子闩锁。基于0.18μm CMOS工艺,利用TCAD器件模拟仿真软件,开展CMOS反相器的单粒子闩锁效应研究。结合单粒子闩锁效应的触发机制,分析粒子入射位置、工作电压、工作温度、有源区距阱接触距离、NMOS和PMOS间距等因素对SEL敏感性的影响,并通过工艺加固得出最优的设计结构。重离子试验表明,采用3.2μm外延工艺,可提高SRAM电路抗SEL能力,当L1、L2分别为0.86μm和0.28μm时,其单粒子闩锁阈值高达99.75 Me V·cm2/mg。

The high-energy particles of large quantities from outer space may lead to Single Event Latch-up（SEL） in CMOS devices. The paper conducts studies on SEL for CMOS inverter using 0.18 μm CMOS technology and the TCAD method. The triggering mechanism of SEL is at first discussed for further analysis on particle incident position, voltage, temperature, distance between active region and body, NMOS and PMOS spacing, as well as radiation-hardened process. Then the optimal structure is obtained. The heavy ion test performed thereafter shows that in the 3.2 μm epitaxial process the SRAM circuit has a high LET threshold of 99.75 Me V·cm^2/mg with L1= 0.86 μm and L2= 0.28 μm.