基于FPGA的CRC查表法设计及优化

Design and optimization of CRC look-up table method based on the FPGA

循环冗余校验Cyclic Redundancy Checks(CRC)具有检错能力极强,开销小,易于用编码器及检测电路实现,远远优于奇偶校验及算术和校验等方式的特点,故在串行通信中添加CRC校验可保证通信的有效性。而FPGA具有灵活稳定,快速高效的特点,故用VHDL实现CRC查表法设计并对其优化分析,使其在串行通信中具有良好的稳定性,提高数据传输的准确性。

Cyclic redundancy check（CRC） has the strong ability of error detection,small overhead,easy to use the encoder and the realization of detection circuit,which is much better than the parity and arithmetic and calibration method,as a result,the characteristics of the CRC check is added in the serial communication which can ensure the effectiveness of communication.And the FPGA is featured with flexible and stable,rapid and efficient characteristics,so the design with VHDL realization of CRC look-up table method and the optimization analysis make it have good stability in serial communication,and the accuracy of the data transmission is improved.