时钟树低功耗设计

Low-power clock tree design

功耗和性能是芯片设计中两项重要的指标,为了满足低功耗的芯片设计要求,IC设计者在芯片设计采用各种低功耗技术。本文提出一种基于寄存器状态的时钟网络的构造方法,它以时钟树中网络节点的节点差异为参数建模,与常规方法相比,此算法可以有效降低门控信号的翻转次数,大幅降低时钟网络的功耗。

Power consumption and performance is two important indicators in the chip design, in order to satisfy the requirement of the low power consumption chip design, IC designer in chip design used in a variety of low power technology. This paper proposed a method to construct based on the state of the register clock network, it for network nodes in the clock tree node difference for parametric modeling, compared with conventional methods, this algorithm can effectively reduce the gating signal frequency flip, greatly reduce power dissipation in clock network.