基于FPGA的RAW图像饱和校正的实现

Implementation of Estimating Saturated Pixel Values Based on FPGA

图像饱和会造成图像的颜色和亮度失真。为了改善图像的质量,论文在现有的算法基础上用FPGA实现了RAW图像饱和校正算法。图像单通道饱和校正时使用了现有贝叶斯算法进行估计,而对图像多通道饱和校正时论文设计了一种环形的硬件结构来实现颜色通道按照顺序处理机制的整个流程,不论哪种校正顺序均能在该环形结构上正确运行。论文算法用VHDL语言编写工程并在Altera Cyclone系列芯片EP4GX150DF31C8上用软件仿真实现,时钟频率最大可以达到110MHz。通过协仿真发现,论文硬件算法可以快速实现对图像饱和像素的校正。论文硬件算法可作为单独的硬件模块植入相机内部进行实时的饱和像素校正。

Pixel saturation is very common in digital color imaging,which will result in the artifact of color splash.In order to improve image quality,this paper presents a hardware implementation in a FPGA circuit of an algorithm to estimate saturated pixels in RAW image.For the 1-channel saturation,the Bayesian estimation is realized using simple digital circuits and memory.For the 2-channel and 3-channel saturation,a ring structure is designed to handle the saturated color channels in the order obtained previously.Whatever the order of the color channels is,the image data can be processed properly by the ring structure.The design has been specified in VHDL targeted on an Altera Cyclone EP4CGX150DF31C8 based FPGA and verified for functional correctness by software simulation,and the fmax can reach 100 MHz.Co-simulation shows that the proposed method in hardware implementation has estimated the saturated pixels fast.The hardware algorithm can be embedded inside the camera to realize correcting saturated pixels in real time.