一种低噪声亚采样锁相环的设计

Design of a low noise sub-sampling phase locked loop

介绍了一种2.4 GHz的低噪声亚采样锁相环。环路锁定是利用亚采样鉴相器对压控振荡器的输出进行采样。不同于传统电荷泵锁相环,由于在锁定状态下没有分频器的作用,由鉴相器和电荷泵所产生的带内噪声不会被放大N2倍,从而会使锁相环的带内噪声极大程度地减小。在输出电压摆幅相同的情况下,压控振荡器采用NMOS-PMOS互补结构降低了锁相环的功耗。锁相环的设计在TSMC 180 nm CMOS工艺下完成,在1.8 V的供电电压下,锁相环功耗为7.2 m W。在偏移载波频率200k Hz处,环路的带内噪声为-124 d Bc/Hz。

A 2. 4 GHz low noise sub-sampling phase-locked loop（ SSPLL） is presented in this paper. The output of Voltage-Controlled Oscillator（ VCO） is sampled by sub-sampling phase-detector（ SSPD） during phase locking. In contrast to the classical charge pump phase-locked loop（ CPPLL）,the inband noise contributed by phase detector and charge pump（ PD / CP） is not multiplied by N2 since the frequency divider is not needed in the locked state in SSPLL. The inband noise of PLL is decreased obviously. In the case of the same output voltage swing,a NMOS-PMOS complimentary topology VCO can decrease the power dissipation to some extent. The SSPLL is implemented in TSMC 180 nm CMOS process. It consumes 7. 2 m W under the supply voltage of 1. 8 V and the inband noise is-124 d Bc / Hz at offset carrier frequency of 200 k Hz.