期刊文献+

基于Han-Carlson结构的加法器优化设计 被引量:1

An Optimal Design for Han Carlson Parallel Prefix Adder
下载PDF
导出
摘要 Han-Carlson结构是介于Kogge-Stone结构和Brent-Kung结构之间的一种并行前缀加法器,并且结合了两种结构的优势.基于Han-Carlson结构并行前缀加法器,对其结构特点进行研究分析,在延时和面积上进行折中选择,提出了一种优化方案,牺牲部分延时,减少使用面积以降低功耗.将其与未优化的Han-Carlson加法器以及混合加法器进行对比后表明,该优化方案成功减少了使用面积,降低了功耗. Han-Carlson parallel-prefix adder is a combination of Kogge-Stone adder and Brent-Kung adder's advantages. This paper proposes a method of optimization based on Han-Carlson parallel-prefix topology. Sacrificing part of the delay and reducing the use of area to reduce power consumption. Comparing with unoptimized Han- Carlson parallel-prefix adder and mixed adders based on Han-Carlson parallel-prefix adder, the proposed method is succeed to reduce the using area and power.
作者 刘加东 李磊 LIU Jia-dong LI Lei(Research Institute Electronic Science and Technology, University of Electronic Science and Technology of China, Chengdu 611731, China)
出处 《微电子学与计算机》 CSCD 北大核心 2017年第3期79-81,共3页 Microelectronics & Computer
关键词 并行前缀加法器 Han-Carlson结构 优化 面积 功耗 parallel-prefix adder Han-Carlsom optimization area power
  • 相关文献

参考文献4

二级参考文献25

  • 1王骞,丁铁夫.一种稀疏树加法器及结构设计[J].电子器件,2005,28(2):312-314. 被引量:2
  • 2崔晓平,王成华.二级进位跳跃加法器的优化方块分配[J].北京航空航天大学学报,2007,33(4):495-499. 被引量:3
  • 3Sklansky J. Conditional sum addition logic [J]. IRE Trans Electron Computers, 1960, EC-9(6) :226-231.
  • 4Brent R P, Kung H T. A regular layout for parallel adders [J]. IEEE Fransactions Computers, 1982,31(3):260-264.
  • 5Kogge P M, Stone H S. A parallel algorithm for efficient solution of a general class of recurrence equations[J]. IEEE Trans Computers, 1973, 22(8) : 786-793.
  • 6Matthew M Ziegler, Mircea R StanA. Unified design space for regular parallel prefix adders[J]. Design Au- tomation and Test in Europe Conference and Exhibi- tion, 2004(2) : 1386-1387.
  • 7Zhu Haikun, Cheng Chungkuan, Ronald Graham. Con- structing zero-deficiency parallel prefix adder of mini- mum Depth[J]. ASP-DAC, 2005(2) : 883- 888.
  • 8Reto Zimmermann. Binary Adder Architecture for Cell- Based VLSI and their Synthesis [D]. Zurich: Swiss Federal Institute of Technology, 1997.
  • 9勒战鹏.高速浮点加法运算单元的研究与实现[D].西安:西北工业大学,2006.
  • 10Hanspeter Kunz and Reto Zimmermann. High-Performance Adder Circuit Generators in Parameterized Structural VHDL[R]. Technical Report No. 96/7, August 1996

共引文献9

同被引文献5

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部